fpga

Research and Teaching

Contact to the webmaster: Jakub Šťastný, stastnj1<at>seznam<dot>cz
(c)2005-11 Jakub Šťastný
page last updated on the 6th of February, 2011

Reklama! Reklama! Reklama! Reklama! Reklama!
Máte zajímavý výzkumný problém, potřebujete na FPGA navrhnout strukturu pro číslicové zpracování signálu či podobné účely? Pak můžete využít možnosti zadat na našem pracovišti diplomovou či bakalářskou práci! Více viz níže.
Do you have an interesting research problem, do you need to design an FPGA system? You can ask our students and let them to solve it in the frame of their bachelor or diploma theses, then! See below for more information.
Reklama! Reklama! Reklama! Reklama! Reklama!

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General Documents, Basic Course in Circuit Theory (Teorie Obvodů)

Circuit Theory I & II - introduction to theoretical electrotechnics (just giving exercises, not lecturing)
- various links to matherials for students (mostly in Czech):
General-purpose texts for students
- Pár rad - in Czech; how to prepare documents and presentations
- A WikiBook on LaTeX - a very nice reference

Brain-Computer Interface (BCI), EEG classification

Various links to materials
- Principles and Applications of Bioelectric and Biomagnetic Fields - COMPLETE BOOK
- Atlasy mozku, anatomické informace
- Kohonen neural network demo - Java interactive applet (in Czech)
Lectures - BMI courses
- Lectures for the BMI course, in Czech

Design of DSP systems on FPGA

Lectures - materials

FPGA Laboratory - important documents
- IP core datasheet example template - MS Word (bleah!)
- Research report document template for MS Word
- Document template for the text documents - Open Office 3.x
- Document template for the text documents - LaTeX
- SOURCE: OBLIGATORY template header for all design files
- rules for the work in the FPGA laboratory (in Czech)
Software & hardware HOWTOs and design examples - for our kits and software

Simulation software

ModelSim Resources (documents, presentations)

Implementation software

SPARTAN 2 (XC2S600E-6FG456C) kit
- HOWTO: ISE full environment, Spartan 2 board settings (in Czech)
- DE: 7 segment display (contains two examples: combinatorial decoder - BIN number on switches is converted to 7 seg VHDL + UCF file and sequential design: counter with prescaler which counts from 0 up to F and displays the numbers on the 7 seg LED. There are again two files there - .vhd and the appropriate .ucf)
- DE: DA converter demo - just DAC controlling
  - DE: DA converter 1 demo - square wave generation, VHDL file. To work with the demo the constraint file is required as well - see link below.
  - DE: DA converter 1 demo - square wave generation, UCF file. Pad constraints for DAC 1 and Spartan kit.
- DE: AD - DA converter demo
  - Input ADC voltage range: 2Vpp for full_scale off, 3Vpp for full scale on
  - Output DAC voltage range: 0x000 -> 1.5V, 0xFFF -> 3.5V (DC offset 2.5V, 2Vpp)
  - AD-DA demo, vhdl source file
  - AD-DA demo, ucf source file
- LEDs & buttons pads - UCF file
- For advanced users: place and route batch file for Precision/Leonardo synthesized design

Virtex II (XC2V1000FG456-4C) kit
- DE: 7 segment display - combinatorial design example
  - VHDL file
  - UCF file
- DE: 7 segment display - sequential design example
  - VHDL file
  - UCF file
- DE: DA converter demo
  - VHDL file
  - UCF file
- DE: AD-DA converter demo
  - AD-DA demo, vhdl source file
  - AD-DA demo, ucf source file
Ready-to-use IP cores - soft macro blocks and designs + design support
- 8th order systolic moving average filter with parallel arithmetic implementation (IP core macro block for future use in research and teaching) (author Lukáš Ručkay)
- Demo of UART XILINX FPGA macro + Matlab communication environment (author Marek Bártů)
- FFT butterfly (author Petr Rašek)
- IIR biquadratic filter macro - IP core (author Lukáš Ručkay)
- LED Controller - CPU Peripheral block
- PC to FPGA kit board communication protocol. (author Marek Bártů)
- PicoCTRL - a simple microprogrammable controller core (author Petr Bílý)
- Pulse-Width Modulator IP core
- Serial arithmetic IP cores
- Simple MAC unit + verification support & Matlab model IP core (author Lukáš Ručkay)
- Verification Environment and documentation (author Lukáš Ručkay, Tomáš Kubec)
- Voice Activity Detector IP block
- VGA controller - proof of concept demo (author David Hradecký)
- VGA controller 2 - 320x200 canvas area, 8 colours palette supported (author Tomáš Kubec)